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1/23 not for new design april 2001 this is information on a product still in production but not recommended for new designs. m28010 1 mbit (128k x 8) parallel eeprom with software data protection n fast access time: 100 ns n single supply voltage: 4.5 v to 5.5 v for m28010 2.7 v to 3.6 v for m28010-w 1.8 v to 2.4 v for m28010-r n low power consumption n fast byte and page write (up to 128 bytes) n enhanced write detection and monitoring: data polling toggle bit page load timer status n jedec approved bytewide pin-out n software data protection n hardware data protection n software chip erase n 100000 erase/write cycles (minimum) n data retention (minimum): 10 years description the m28010 devices consist of 128kx8 bits of low power, parallel eeprom, fabricated with stmicroelectronics' proprietary double polysilicon cmos technology. the devices offer fast access time, with low power dissipation, and require a single voltage supply (5v, 3v or 2v, depending on the option chosen). figure 1. logic diagram ai02221 17 a0-a16 w dq0-dq7 v cc m28010 g e v ss 8 table 1. signal names a0-a16 address input dq0-dq7 data input / output w write enable e chip enable g output enable v cc supply voltage v ss ground pdip32 (ba) plcc32 (ka) tsop32 (na) 8 x 20 mm 32 1
m28010 2/23 figure 2a. dip connections note: 1. du = do not use figure 2b. plcc connections note: 1. du = do not use a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a14 a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 du v cc ai02222 m28010 8 1 15 16 4 5 6 7 9 10 11 12 13 14 32 31 30 27 26 25 24 23 22 21 20 19 18 17 a15 du w a16 2 3 29 28 ai02223 du a8 a10 dq4 17 a0 a7 dq0 dq1 dq2 dq6 dq3 a6 a3 a2 a1 a5 a4 9 w a9 1 a16 a11 a14 a12 dq7 32 du v cc m28010 a15 a13 dq5 g e 25 v ss figure 2c. tsop connections note: 1. du = do not use a2 a1 a0 a6 a3 a5 a4 a9 a11 dq7 a8 g e dq5 dq0 dq1 dq3 dq4 dq6 a13 w a15 a7 a14 v cc a12 ai02224 m28010 8 1 9 16 17 24 25 32 v ss a10 dq2 du a16 du the device has been designed to offer a flexible microcontroller interface, featuring both hardware and software hand-shaking, with data polling and toggle bit. the device supports a 128 byte page write operation. software data protection (sdp) is also supported, using the standard jedec algorithm. the m28010 is designed for applications requiring as much as 100,000 write cycles and ten years of data retention. the organization of the data in a 4 byte (32-bit) awordo format leads to significant savings in power consumption. once a byte has been read, subsequent byte read cycles from the same awordo (with addresses differing only in the two least significant bits) are fetched from the previously loaded read buffer, not from the memory array. as a result, the power consumption for these subsequent read cycles is much lower than the power consumption for the first cycle. by careful design of the memory access patterns, a 50% reduction in the power consumption is possible. signal description the external connections to the device are summarized in table 1, and their use in table 3. addresses (a0-a16). the address inputs are used to select one byte from the memory array during a read or write operation. data in/out (dq0-dq7). the contents of the data byte are written to, or read from, the memory array through the data i/o pins. chip enable (e). the chip enable input must be held low to enable read and write operations. when chip enable is high, power consumption is reduced. output enable (g). the output enable input controls the data output buffers, and is used to initiate read operations.
3/23 m28010 figure 3. block diagram ai02225 address latch a7-a16 (page address) x decode control logic 1mbit array address latch a0-a6 i/o buffers v pp gen latch page y decode sense page & data latch e g w dq0-dq7 ecc (1) & multiplexer v read gen references programming state machine table 2. absolute maximum ratings 1 note: 1. except for the rating aoperating temperature rangeo, stresses above those listed in the table aabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. refer also to the st sure program and other relevant quality documents. 2. mil-std-883c, 3015.7 (100 pf, 1500 w ) symbol parameter value unit t a ambient operating temperature 40 to 85 c t stg storage temperature 65 to 150 c v cc supply voltage 0.3 to v ccmax +1 v v io input or output voltage (except a9) 0.3 to v cc +0.6 v v i input voltage 0.3 to 4.5 v v esd electrostatic discharge voltage (human body model) 2 2000 v
m28010 4/23 table 3. operating modes 1 note: 1. x = v ih or v il . mode e g w dq0-dq7 read v il v il v ih data out write v il v ih v il data in stand-by / write inhibit v ih x x hi-z write inhibit x x v ih data out or hi-z write inhibit x v il x data out or hi-z output disable x v ih x hi-z write enable (w). the write enable input controls whether the addressed location is to be read, from or written to. device operation in order to prevent data corruption and inadvertent write operations, an internal v cc comparator inhibits the write operations if the v cc voltage is lower than v wi (see table 4a to table 4c). once the voltage applied on the v cc pin goes over the v wi threshold (v cc >v wi ), write access to the memory is allowed after a time-out t puw ,as specified in table 4a to table 4c. further protection against data corruption is offered by the e and w low pass filters: any glitch, on the e and w inputs, with a pulse width less than 10 ns (typical) is internally filtered out to prevent inadvertent write operations to the memory. table 4a. power-up timing 1 for m28010 (5v range) (t a = 40 to 85 c; v cc = 4.5 to 5.5 v) note: 1. sampled only, not 100% tested. table 4b. power-up timing 1 for m28010-w (3v range) (t a = 40 to 85 c; v cc = 2.7 to 3.6 v) note: 1. sampled only, not 100% tested. table 4c. power-up timing 1 for m28010-r (2v range) (t a = 40 to 85 c; v cc = 1.8 to 2.4 v) note: 1. sampled only, not 100% tested. symbol parameter min. max. unit t pur time delay to read operation 5 ms t puw time delay to write operation (once v cc v wi ) 5ms v wi write inhibit threshold 3.0 4.2 v symbol parameter min. max. unit t pur time delay to read operation 5 ms t puw time delay to write operation (once v cc v wi )5 ms v wi write inhibit threshold 2.0 2.6 v symbol parameter min. max. unit t pur time delay to read operation 5 ms t puw time delay to write operation (once v cc v wi )5 ms v wi write inhibit threshold 1.2 1.7 v
5/23 m28010 figure 4. software data protection enable algorithms (with or without memory write) wait for write completion (t q5hq5x ) wait for write completion (t q5hq5x ) wait for write completion (t q5hq5x ) ai02227b write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h sdp is set page write timing sdp is disabled and application needs to enable it, and write data time out (t wlq5h ) data has been written and sdp is enabled sdp is disabled and application needs to enable it write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h page write timing data has been written and sdp is enabled time out (t wlq5h ) write data in any addresses within one page write is enabled write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h page write timing time out (t wlq5h ) write data in any addresses within one page write is enabled read the device is accessed like a static ram. when e and g are low, and w is high, the contents of the addressed location are presented on the i/o pins. otherwise, when either g or e is high, the i/o pins revert to their high impedance state. write write operations are initiated when both w and e are low and g is high. the device supports both w-controlled and e-controlled write cycles (as shown in figure 12 and figure 13). the address is latched during the falling edge of w or e (which ever occurs later) and the data is latched on the rising edge of w or e (which ever occurs first). after a delay, t wlq5h , that cannot be shorter than the value specified in table 9a to table 9c, the internal write cycle starts. it continues, under internal timing control, until the write operation is complete. the commencement of this period can be detected by reading the page load timer status on dq5. the end of the internal write cycle
m28010 6/23 figure 5. software data protection disable algorithms (with or without memory write) wait for write completion (t q5hq5x ) wait for write completion (t q5hq5x ) ai02226b write aah in address 5555h write 55h in address 2aaah write 80h in address 5555h sdp is disabled write aah in address 5555h write 55h in address 2aaah write 20h in address 5555h page write timing sdp is enabled and application needs to disable it time out (t wlq5h ) write aah in address 5555h write 55h in address 2aaah write 80h in address 5555h data has been written and sdp is disabled write aah in address 5555h write 55h in address 2aaah write 20h in address 5555h page write timing sdp is enabled and application needs to write data time out (t wlq5h ) write data in any addresses within one page physical write instructions can be detected by reading the status of the data polling and the toggle bit functions on dq7 and dq6. page write the page write mode allows up to 128 bytes to be written on a single page in a single go. this is achieved through a series of successive write operations, no two of which are separated by more than the t wlq5h value (as specified in table 9a to table 9c). the page write can be initiated during any byte write operation. following the first byte write instruction, the host may send another address and data with a minimum data transfer rate of: 1/t wlq5h . the internal write cycle can start at any instant after t wlq5h . once initiated, the write operation is internally timed, and continues, uninterrupted, until completion. all bytes must be located on the same page address (a16-a7 must be the same for all bytes). otherwise, the page write operation is not executed. the page write abort event is indicated to the application via dq1 (as described on page 8). as with the single byte write operation, described above, the dq5, dq6 and dq7 lines can be used to detect the beginning and end of the internally controlled phase of the page write cycle. software data protection (sdp) the device offers a software-controlled write- protection mechanism that allows the user to inhibit all write operations to the device, including chip erase. this can be useful for protecting the
7/23 m28010 memory from inadvertent write cycles that may occur during periods of instability (uncontrolled bus conditions when excessive noise is detected, or when power supply levels are outside their specified values). by default, the device is shipped in the aunprotectedo state: the memory contents can be freely changed by the user. once the software data protection mode is enabled, all write commands are ignored, and have no effect on the memory contents. the device remains in this mode until a valid software data protection disable sequence is received. the device reverts to its aunprotectedo state. the status of the software data protection (enabled or disabled) is represented by a non- volatile latch, and is remembered across periods of the power being off. the software data protection enable command consists of the writing of three specific data bytes to three specific memory locations (each location being on a different page), as shown in figure 4. similarly, to disable the software data protection, the user has to write specific data bytes into six different locations, as shown in figure 5. this complex series of operations protects against the chance of inadvertent enabling or disabling of the software data protection mechanism. when sdp is enabled, the memory array can still have data written to it, but the sequence is more complex (and hence better protected from inadvertent use). the sequence is as shown in figure 5. this consists of an unlock key, to enable the write action, at the end of which the sdp continues to be enabled. this allows the sdp to be enabled, and data to be written, within a single write cycle (t wc ). figure 6. software chip erase algorithm wait for write completion (t q5hq5x ) ai02236c write aah in address 5555h write 55h in address 2aaah write 80h in address 5555h whole array has been set to ffh write aah in address 5555h write 55h in address 2aaah write 10h in address 5555h page write timing time out (t wlq5h ) figure 7. status bit assignment figure 8. software data protection status read algorithm ai02486b dp tb plts x x x pwa sdp dp tb plts x pwa sdp dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 = data polling = toggle bit = page load timer status = undefined = page write abort = software data protection ai02237b write aah in address 5555h write 55h in address 2aaah write 20h in address 5555h normal user mode read sdp on dq0 write xxh in address xxxxh page write timing
m28010 8/23 software chip erase the device can be erased (with all bytes set to ffh) by using a six-byte software command code. this operation can be initiated only if the user loads, with a page write addressing mode, six specific data bytes to six specific locations (as shown in figure 6). the complexity of the sequence has been designed to guard against inadvertent use of the command. status bits the devices provide five status bits (dq7, dq6, dq5, dq1 and dq0) for use during write operations. these allow the application to use the write time latency of the device for getting on with other work. these signals are available on the i/o port bits dq7, dq6, dq5, dq1 and dq0 (but only during the internal write cycle, t q5hq5x ). data polling bit (dq7). the internally timed write cycle starts as soon as t wlq5h (defined in table 9a to table 9c) has elapsed since the previous byte was latched in to the memory. the value of the dq7 bit of this last byte, is used as a signal throughout this write operation: it is inverted while the internal write operation is underway, and is inverted back to its original value once the operation is complete. toggle bit (dq6). the device offers another way for determining when the internal write cycle is running. during the internal write cycle, dq6 toggles from '0' to '1' and '1' to '0' (the first read value being '0') on subsequent attempts to read any byte of the memory. when the internal write cycle is complete, the toggling is stopped, and the values read on dq7-dq0 are those of the addressed memory byte. this indicates that the device is again available for new read and write operations. page load timer status bit (dq5). an internal timer is used to measure the period between successive write operations, up to t wlq5h (defined in table 9a to table 9c). the dq5 line is held low to show when this timer is running (hence showing that the device has received one write operation, and is waiting for the next). the dq5 line is held high when the counter has overflowed (hence showing that the device is now starting the internal write to the memory array). page write abort bit (dq1). during a page write operation, the a16 to a7 signals should be kept constant. they should not change while successive data bytes are being transferred to the internal latches of the memory device. if a change occurs on any of the pins, a16 to a7, during the page write operation (that is, before the falling edge of w or e, which ever occurs later), the internal write cycle is not started, and the internal circuitry is completely reset. the abort signal can be observed on the dq1 pin, using a normal read operation. this can be performed at any time during the byte load cycle, t wlq5h , or while the w input is being held high between two load cycles. the default value of dq1 is initially set to '0' and changes to '1' if the internal circuitry has detected a change on any of the address pins a16 to a7. this pwa bit can be checked regardless of whether software data protection is enabled or disabled. table 5a. read mode dc characteristics for m28010 (5v range) (t a = 40 to 85 c; v cc = 4.5 to 5.5 v) note: 1. all inputs and outputs open circuit. symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 5 m a i lo output leakage current 0 v v out v cc 5 m a i cc 1 supply current (cmos inputs) e=v il ,g=v il , f = 0.1 mhz 2ma e=v il ,g=v il , f = 5 mhz 22 ma e=v il ,g=v il , f = 10 mhz 40 ma i cc1 1 supply current (stand-by) cmos e > v cc 0.3v 50 m a v il input low voltage 0.3 0.8 v v ih input high voltage 2 v cc + 0.3 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = 400 m a 2.4 v
9/23 m28010 table 5b. read mode dc characteristics for m28010-w (3v range) (t a = 40 to 85 c; v cc = 2.7 to 3.6 v) note: 1. all inputs and outputs open circuit. table 5c. read mode dc characteristics for m28010-r (2v range) (t a = 40 to 85 c; v cc = 1.8 to 2.4 v) note: 1. all inputs and outputs open circuit. symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 5 m a i lo output leakage current 0v v out v cc 5 m a i cc 1 supply current (cmos inputs) e=v il ,g=v il , f = 0.1 mhz 2ma e=v il ,g=v il ,f=5mhz 15 ma e=v il ,g=v il , f = 10 mhz 26 ma i cc1 1 supply current (stand-by) cmos e>v cc 0.3 v 30 m a v il input low voltage 0.3 0.6 v v ih input high voltage 2 v cc + 0.3 v v ol output low voltage i ol = 1.6 ma 0.45 v v oh output high voltage i oh = 100 m a 2.4 v symbol parameter test conditio n min. max. unit i li input leakage current 0v v in v cc 5 m a i lo output leakage current 0v v out v cc 5 m a i cc 1 supply current (cmos inputs) e=v il ,g=v il , f = 0.1 mhz, v cc = 2.4 v 2ma e=v il ,g=v il , f = 5 mhz, v cc = 2.4 v 12 ma i cc1 1 supply current (stand-by) cmos e>v cc 0.3 v 30 m a v il input low voltage 0.3 0.2 v v ih input high voltage v cc 0.3 v cc +0.3 v v ol output low voltage i ol = 0.4 ma 0.15 v v oh output high voltage i oh = 100 m av cc 0.15 v software data protection bit (dq0). reading the sdp bit (dq0) allows the user to determine whether the software data protection mode has been enabled (sdp=1) or disabled (sdp=0). the sdp bit (dq0) can be read by using a dedicated algorithm (as shown in figure 8), or can be combined with the reading of the dp bit (dq7), tb bit (dq6) and plts bit (dq5).
m28010 10/23 table 6. input and output parameters 1 (t a =25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min. max. unit c in input capacitance v in =0v 6 pf c out output capacitance v out =0v 12 pf table 7. ac measurement conditions input rise and fall times 5ns input pulse voltages 0 v to v cc input and output timing ref. voltages v cc /2 figure 9. ac testing input output waveforms ai02228 v cc 0v v cc /2 figure 10. ac testing equivalent load circuit ai02578 out c l = 30pf c l includes jig capacitance i ol device under test i oh table 8a. read mode ac characteristics for m28010 (5v range) (t a = 40 to 85 c; v cc = 4.5 to 5.5 v) note: 1. output hi-z is defined as the point at which data is no longer driven. symbol alt. parameter test condi t ion m28010 unit 10 12 min max min max t avqv t acc address valid to output valid e=v il , g=v il 100 120 ns t elqv t ce chip enable low to output valid g=v il 100 120 ns t glqv t oe output enable low to output valid e=v il 40 45 ns t ehqz 1 t df chip enable high to output hi-z g=v il 0 40 0 45 ns t ghqz 1 t df output enable high to output hi-z e=v il 0 40 0 45 ns t axqx t oh address transition to output transition e=v il , g=v il 00ns
11/23 m28010 table 8b. read mode ac characteristics for m28010-w (3v range) (t a = 40 to 85 c; v cc = 2.7 to 3.6 v) note: 1. output hi-z is defined as the point at which data is no longer driven. table 8c. read mode ac characteristics for m28010-r (2v range) (t a = 40 to 85 c; v cc = 1.8 to 2.4 v) note: 1. output hi-z is defined as the point at which data is no longer driven. symbol alt. parameter test condi t ion m28010-w unit 10 12 15 min max min max min max t avqv t acc address valid to output valid e=v il , g=v il 100 120 150 ns t elqv t ce chip enable low to output valid g=v il 100 120 150 ns t glqv t oe output enable low to output valid e = v il 70 80 100 ns t ehqz 1 t df chip enable high to output hi-z g = v il 050060070ns t ghqz 1 t df output enable high to output hi-z e=v il 050060070ns t axqx t oh address transition to output transition e=v il , g=v il 000ns symbol alt. parameter test condi t ion m28010-r unit 20 25 min max min max t avqv t acc address valid to output valid e=v il , g=v il 200 250 ns t elqv t ce chip enable low to output valid g=v il 200 250 ns t glqv t oe output enable low to output valid e = v il 80 90 ns t ehqz 1 t df chip enable high to output hi-z g = v il 0 50 0 60 ns t ghqz 1 t df output enable high to output hi-z e=v il 0 50 0 60 ns t axqx t oh address transition to output transition e=v il , g=v il 00ns
m28010 12/23 table 9a. write mode ac characteristics for m28010 (5v range) (t a = 40 to 85 c; v cc = 4.5 to 5.5 v) symbol alt. parameter test condit ion m28010 unit min max t avwl t as address valid to write enable low e = v il ,g=v ih 0ns t avel t as address valid to chip enable low g=v ih ,w=v il 0ns t elwl t ces chip enable low to write enable low g = v ih 0ns t ghwl t oes output enable high to write enable low e=v il 0ns t ghel t oes output enable high to chip enable low w=v il 0ns t wlel t wes write enable low to chip enable low g=v ih 0ns t wlax t ah write enable low to address transition 70 ns t elax t ah chip enable low to address transition 70 ns t eleh t wp chip enable low to chip enable high 100 ns t wheh t ceh write enable high to chip enable high 0 ns t whgl t oeh write enable high to output enable low 0 ns t ehwh t weh chip enable high to write enable high 0 ns t whdx t dh write enable high to input transition 0 ns t ehdx t dh chip enable high to input transition 0 ns t whwl t wph write enable high to write enable low 50 ns t wlwh t wp write enable low to write enable high 100 ns t wlq5h t blc time-out after the last byte write 150 m s t q5hq5x t wc byte write cycle time 5 ms page write cycle time (up to 128 bytes) 10 ms t dvwh t ds data valid before write enable high 50 ns t dveh t ds data valid before chip enable high 50 ns figure 11. read mode ac waveforms (with write enable, w, high) note: 1. write enable (w) = v ih ai02229 valid tavqv taxqx tglqv tehqz tghqz data out a0-a16 e g dq0-dq7 telqv hi-z
13/23 m28010 table 9b. write mode ac characteristics for m28010-w (3v range) (t a = 40 to 85 c; v cc = 2.7 to 3.6 v) symbol alt. parameter test condit ion m28010-w unit min max t avwl t as address valid to write enable low e=v il ,g=v ih 0ns t avel t as address valid to chip enable low g=v ih ,w=v il 0ns t elwl t ces chip enable low to write enable low g=v ih 0ns t ghwl t oes output enable high to write enable low e = v il 0ns t ghel t oes output enable high to chip enable low w=v il 0ns t wlel t wes write enable low to chip enable low g = v ih 0ns t wlax t ah write enable low to address transition 70 ns t elax t ah chip enable low to address transition 70 ns t eleh t wp chip enable low to chip enable high 100 ns t wheh t ceh write enable high to chip enable high 0 ns t whgl t oeh write enable high to output enable low 0 ns t ehwh t weh chip enable high to write enable high 0 ns t whdx t dh write enable high to input transition 0 ns t ehdx t dh chip enable high to input transition 0 ns t whwl t wph write enable high to write enable low 50 ns t wlwh t wp write enable low to write enable high 100 ns t wlq5h t blc time-out after the last byte write 150 m s t q5hq5x t wc byte write cycle time 5 ms page write cycle time (up to 128 bytes) 10 ms t dvwh t ds data valid before write enable high 80 ns t dveh t ds data valid before chip enable high 80 ns
m28010 14/23 table 9c. write mode ac characteristics for m28010-r (2v range) (t a = 40 to 85 c; v cc = 1.8 to 2.4 v) symbol alt. parameter test condit ion m28010-r unit min max t avwl t as address valid to write enable low e=v il ,g=v ih 0ns t avel t as address valid to chip enable low g=v ih ,w=v il 0ns t elwl t ces chip enable low to write enable low g=v ih 0ns t ghwl t oes output enable high to write enable low e=v il 0ns t ghel t oes output enable high to chip enable low w=v il 0ns t wlel t wes write enable low to chip enable low g=v ih 0ns t wlax t ah write enable low to address transition 120 ns t elax t ah chip enable low to address transition 120 ns t eleh t wp chip enable low to chip enable high 120 ns t wheh t ceh write enable high to chip enable high 0 ns t whgl t oeh write enable high to output enable low 0 ns t ehwh t weh chip enable high to write enable high 0 ns t whdx t dh write enable high to input transition 0 ns t ehdx t dh chip enable high to input transition 0 ns t whwl t wph write enable high to write enable low 100 ns t wlwh t wp write enable low to write enable high 120 ns t wlq5h t blc time-out after the last byte write 150 m s t whrh t wc byte write cycle time 5 ms page write cycle time (up to 128 bytes) 10 ms t dvwh t ds data valid before write enable high 120 ns t dveh t ds data valid before chip enable high 120 ns
15/23 m28010 figure 12. write mode ac waveforms (write enable, w, controlled) figure 13. write mode ac waveforms (chip enable, e, controlled) ai02230 valid tavwl a0-a16 e g dq0-dq7 data in w twlax telwl tghwl twheh twhgl twlwh twhwl twhdx tdvwh ai02231 valid tavel a0-a16 e g dq0-dq7 data in w telax tghel twlel tehgl tehdx tdveh teleh tehwh
m28010 16/23 figure 14. page write mode ac waveforms (write enable, w, controlled) figure 15. software protected write cycle waveforms note: 1. a16 to a7 must specify the same page address during each high-to-low transition of w (or e). g must be high only when w and e are both low. tq5hq5x ai02829b a0-a16 e g dq0-dq7 (in) w addr 0 dq5 (out) addr 1 addr 2 addr n twlq5h twlwh twhwl byte 0 byte 1 byte 2 byte n ai02233b a7-a16 e g dq0-dq7 w page add 1 twlwh twhwl aah 55h a0h a0-a6 5555h 2aaah 5555h byte add n tdvwh twhdx byte add 0 byte n byte 0
17/23 m28010 figure 16. data polling sequence waveforms figure 17. toggle bit sequence waveforms note: 1. the toggle bit is first set to `0'. ai02234 a0-a16 e g dq7 w dq7 dq7 dq7 dq7 dq7 ready after internal write sequence last byte loaded internal write sequence or time between two consecutive bytes loading address of the last byte of the page write instruction twhgl ai02235 a0-a16 e g dq6 w (1) toggle ready after internal write sequence last byte loaded internal write sequence or time between two consecutive bytes loading address of the last byte of the page write instruction
m28010 18/23 table 10. ordering information scheme note: 1. this temperature range on request only. example: m28010 10 w ka 6 t option t tape & reel packing speed -10 100 ns temperature range -12 120 ns 1 1 0to70 c -15 150 ns 6 40 to 85 c -20 200 ns -25 250 ns operating voltage package blank 4.5 v to 5.5 v ba pdip32 w 2.7 v to 3.6 v ka plcc32 r 1.8 v to 2.4 v na tsop32: 8 x 20mm ordering information devices are shipped from the factory with the memory content set at all `1's (ffh). the notation used for the device number is as shown in table 10. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you.
19/23 m28010 figure 18. pdip32 (ba) note: 1. drawing is not to scale. pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2 table 11. pdip32 - 32 lead plastic dip, 600 mils width, package mechanical data symbol mm inches typ. min. max. typ. min. max. a 5.08 0.200 a1 0.38 0.015 a2 3.56 4.06 0.140 0.160 b 0.38 0.51 0.015 0.020 b1 1.52 0.060 c 0.20 0.30 0.008 0.012 d 41.78 42.04 1.645 1.655 d2 38.10 1.500 e 15.24 0.600 e1 13.59 13.84 0.535 0.545 e1 2.54 0.100 ea 15.24 0.600 eb 15.24 17.78 0.600 0.700 l 3.18 3.43 0.125 0.135 s 1.78 2.03 0.070 0.080 a 0 10 0 10 n32 32
m28010 20/23 table 12. plcc32 - 32 lead plastic leaded chip carrier, rectangular symbol mm inches typ. min. max. typ. min. max. a 2.54 3.56 0.100 0.140 a1 1.52 2.41 0.060 0.095 a2 0.38 0.015 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 12.32 12.57 0.485 0.495 d1 11.35 11.56 0.447 0.455 d2 9.91 10.92 0.390 0.430 e 14.86 15.11 0.585 0.595 e1 13.89 14.10 0.547 0.555 e2 12.45 13.46 0.490 0.530 e 1.27 0.050 f 0.00 0.25 0.000 0.010 r 0.89 0.035 n32 32 nd 7 7 ne 9 9 cp 0.10 0.004 figure 19. plcc32 (ka) note: 1. drawing is not to scale. plcc d ne e1 e 1n d1 nd cp b d2/e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2
21/23 m28010 table 13. tsop32 - 32 lead plastic thin small outline, 8 x 20mm, package mechanical data symbol mm inches typ. min. max. typ. min. max. a 1.20 0.047 a1 0.05 0.17 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.15 0.27 0.006 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 7.90 8.10 0.311 0.319 e 0.50 0.020 l 0.50 0.70 0.020 0.028 a 0 5 0 5 n32 32 cp 0.10 0.004 figure 20. tsop32 (ns) note: 1. drawing is not to scale. tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a
m28010 22/23 table 14. revision history date description of revision 15-feb-2000 i cc1 (max), in read mode dc char table for 5v, changed from 30 m ato50 m a. 28-feb-2000 t dvwh (min) and t dveh (min), in write mode ac char table for 3v, changed from 50 ns to 80 ns 02-apr-2001 data sheet, and product, are anot for new designo
23/23 m28010 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of stmicroelectronics. ? 2001 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http:// www.st.com

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